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250 mhz bandwidth dpd observation receiver ad6641 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features snr = 65.8 dbfs at f in up to 250 mhz at 500 msps enob of 10.5 bits at f in up to 250 mhz at 500 msps (?1.0 dbfs) sfdr = 80 dbc at f in up to 250 mhz at 500 msps (?1.0 dbfs) excellent linearity dnl = 0.5 lsb typical, inl = 0.6 lsb typical integrated 16k 12 fifo fifo readback options 12-bit parallel cmos at 62.5 mhz 6-bit ddr lvds interface sport at 62.5 mhz spi at 25 mhz high speed synchronization capability 1 ghz full power analog bandwidth integrated input buffer on-chip reference, no external decoupling required low power dissipation 695 mw at 500 msps programmable input voltage range 1.18 v to 1.6 v, 1.5 v nominal 1.9 v analog and digital supply operation 1.9 v or 3.3 v spi and sport operation clock duty cycle stabilizer integrated data clock output with programmable clock and data alignment applications wireless and wired broadband communications communications test equipment power amplifier linearization general description the ad6641 is a 250 mhz bandwidth digital predistortion (dpd) observation receiver that integrates a 12-bit 500 msps adc, a 16k 12 fifo, and a multimode back end that allows users to retrieve the data through a serial port (sport), the spi interface, a 12-bit parallel cmos port, or a 6-bit ddr lvds port after being stored in the integrated fifo memory. it is opti- mized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. all necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. the on-chip fifo allows small snapshots of time to be captured via the adc and read back at a lower rate. this reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. the fifo can be operated in several user-programmable modes. in the single capture mode, the adc data is captured when sig- naled via the spi port or the use of the external fill pins. in the continuous capture mode, the data is loaded continuously into the fifo and the fill pins are used to stop this operation. functional block diagram fifo 16k 12 parallel and sport outputs spi control and data reference clock and control vin+ vin? vref sclk, sdio, and csb clk+ clk? dump fill+ fill ? empty sp_sdo sp_sdfs sp_sclk pd[5:0] in ddr lvds mode or pd[11:0] in cmos mode pclk+ full pclk? adc 09813-001 figure 1.
ad6641 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? product highlights ........................................................................... 3 ? specifications..................................................................................... 4 ? dc specifications ......................................................................... 4 ? ac specifications.......................................................................... 5 ? digital specifications ................................................................... 6 ? switching specifications .............................................................. 7 ? spi timing requirements ........................................................... 8 ? absolute maximum ratings.......................................................... 10 ? thermal resistance .................................................................... 10 ? esd caution................................................................................ 10 ? pin configurations and function descriptions ......................... 11 ? typical performance characteristics ........................................... 15 ? equivalent circuits......................................................................... 18 ? spi register map ............................................................................ 20 ? theory of operation ...................................................................... 23 ? fifo operation.......................................................................... 23 ? fifo output interfaces ............................................................. 26 ? configuration using the spi..................................................... 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 4/11revision 0: initial version
ad6641 rev. 0 | page 3 of 28 the data stored in the fifo can be read back based on several user-selectable output modes. the dump pin can be asserted to output the fifo data. the data stored in the fifo can be accessed via a sport, spi, 12-bit parallel cmos port, or 6-bit ddr lvds interface. the maximum output throughput supported by the ad6641 is in the 12-bit cmos or 6-bit ddr lvds mode and is internally limited to 1/8 th of the maximum input sample rate. this corresponds to the maximum output data rate of 62.5 mhz at an input clock rate of 500 msps. the adc requires a 1.9 v analog voltage supply and a differen- tial clock for full performance operation. output format options include twos complement, offset binary format, or gray code. a data clock output is available for proper output data timing. fabri- cated on an advanced sige bicmos process, the device is available in a 56-lead lfcsp and is specified over the industrial temperature range (?40c to +85c). this product is protected by a u.s. patent. product highlights 1. high performance adc core. maintains 65.8 dbfs snr at 500 msps with a 250 mhz input. 2. low power. consumes only 695 mw at 500 msps. 3. ease of use. on-chip 16k fifo allows the user to target the high perfor- mance adc to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. the on-chip refer- ence and sample-and-hold provide flexibility in system design. use of a single 1.9 v supply simplifies system power supply design. 4. serial port control. standard serial port interface supports configuration of the device and customization for the users needs. 5. 1.9 v or 3.3 v spi and serial data port operation.
ad6641 rev. 0 | page 4 of 28 specifications dc specifications avdd = 1.9 v, drvdd = 1.9 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 1. ad6641-500 parameter 1 temp min typ max unit resolution 12 bits accuracy no missing codes full guaranteed offset error full ?2.6 0.0 +1.8 mv gain error full ?6.8 ?2.3 +3.3 % fs differential nonlinearity (dnl) full 0.5 lsb integral nonlinearity (inl) full 0.6 lsb temperature drift offset error full 18 v/c gain error full 0.07 %/c analog inputs (vin) differential input voltage range 2 full 1.18 1.5 1.6 v p-p input common-mode voltage full 1.8 v input resistance (differential) full 1 k input capacitance (differential) 25c 1.3 pf power supply avdd full 1.8 1.9 2.0 v drvdd full 1.8 1.9 2.0 v spi_vddio full 1.8 1.9 3.3 v supply currents i avdd 3 full 300 330 ma i drvdd 3 full 66 80 ma power dissipation 3 full 695 779 mw power-down dissipation full 15 mw standby dissipation full 72 mw standby to power-up time full 10 s 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and information about how these tests were completed. 2 the input range is programmable through the spi, and the range specified reflects the nominal values of each setting. see the spi register map section for additional details. 3 i avdd and i drvdd are measured with a ?1 dbfs, 30 mhz sine input at a rated sample rate.
ad6641 rev. 0 | page 5 of 28 ac specifications avdd = 1.9 v, drvdd = 1.9 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 2. ad6641-500 parameter 1 , 2 temp min typ max unit snr f in = 30 mhz 25c 66.0 dbfs f in = 125 mhz 25c 65.9 dbfs full 65.0 dbfs f in = 250 mhz 25c 65.8 dbfs f in = 450 mhz 25c 65.1 dbfs sinad f in = 30 mhz 25c 66.0 dbfs f in = 125 mhz 25c 65.7 dbfs full 63.8 dbfs f in = 250 mhz 25c 65.3 dbfs f in = 450 mhz 25c 64.6 dbfs effective number of bits (enob) f in = 30 mhz 25c 10.7 bits f in = 125 mhz 25c 10.6 bits f in = 250 mhz 25c 10.5 bits f in = 450 mhz 25c 10.4 bits sfdr f in = 30 mhz 25c 88 dbc f in = 125 mhz 25c 83 dbc full 77 dbc f in = 250 mhz 25c 80 dbc f in = 450 mhz 25c 72 dbc worst harmonic (second or third) f in = 30 mhz 25c ?92 dbc f in = 125 mhz 25c ?77 dbc full ?84 dbc f in = 250 mhz 25c ?80 dbc f in = 450 mhz 25c ?72 dbc worst other harmonic (sfdr excluding second and third) f in = 30 mhz 25c ?90 dbc f in = 125 mhz 25c ?90 dbc full ?77 dbc f in = 250 mhz 25c ?85 dbc f in = 450 mhz 25c ?78 dbc two-tone imd f in1 = 119.8 mhz, f in2 = 125.8 mhz (?7 dbfs, each tone) 25c ?82 dbc analog input bandwidth 25c 1 ghz 1 all ac specifications tested by driving clk+ and clk? differentially. 2 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and information about how these tests were completed.
ad6641 rev. 0 | page 6 of 28 digital specifications avdd = 1.9 v, drvdd = 1.9 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 3. ad6641-500 parameter 1 temp min typ max unit clock inputs (clk) logic compliance full cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage high level input (v ih ) full 0.2 1.8 v p-p low level input (v il ) full ?1.8 ?0.2 v p-p high level input current (i ih ) full ?10 +10 a low level input current (i il ) full ?10 +10 a input resistance (differential) full 8 10 12 k input capacitance full 4 pf logic inputs (spi, sport) logic compliance full cmos logic 1 voltage full 0.8 spi_vddio v logic 0 voltage full 0.2 spi_vddio v logic 1 input current (sdio) full 0 a logic 0 input current (sdio) full ?60 a logic 1 input current (sclk) full 50 a logic 0 input current (sclk) full 0 a input capacitance 25c 4 pf logic inputs (dump, csb) logic compliance full cmos logic 1 voltage full 0.8 drvdd v logic 0 voltage full 0.2 drvdd v logic 1 input current full 0 a logic 0 input current full ?60 a input capacitance 25c 4 pf logic inputs (fill) logic compliance full cmos/lvds/lvpecl internal common-mode bias full 0.9 v differential input voltage high level input (v ih ) full 0.2 1.8 v p-p low level input (v il ) full ?1.8 ?0.2 v p-p high level input current (i ih ) full ?10 +10 a low level input current (i il ) full ?10 +10 a input resistance (differential) full 8 10 12 k input capacitance full 4 pf logic outputs 2 (full, empty) logic compliance full cmos high level output voltage full drvdd ? 0.05 v low level output voltage full drgnd + 0.05 v logic outputs 2 (spi, sport) logic compliance full cmos high level output voltage full spi_vddio ? 0.05 v low level output voltage full drgnd + 0.05 v
ad6641 rev. 0 | page 7 of 28 ad6641-500 parameter 1 temp min typ max unit logic outputs ddr lvds mode (pclk, pd[5:0], pdor) logic compliance full lvds v od differential output voltage full 247 454 mv v os output offset voltage full 1.125 1.375 v parallel cmos mode (pclk, pd[11:0]) logic compliance full cmos high level output voltage full drvdd ? 0.05 v low level output voltage full drgnd + 0.05 v output coding twos complement, gray code, or offset binary (default) 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and information about how these tests were completed. 2 5 pf loading. switching specifications avdd = 1.9 v, drvdd = 1.9 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.5 v, unless otherwise noted. table 4. ad6641-500 parameter 1 temp min typ max unit output data rate maximum output data rate (decimate by 8 at 500 msps sample rate, parallel cmos or ddr lvds mode interface) full 62.5 mhz maximum output data rate (decimate by 8 at 500 msps sample rate, sport mode) full 62.5 mhz pulse width/period (clk) clk pulse width high (t ch ) full 1 ns clk pulse width low (t cl ) full 1 ns rise time (t r ) (20% to 80%) 25c 0.2 ns fall time (t f ) (20% to 80%) 25c 0.2 ns pulse width/period (pclk, ddr lvds mode) pclk pulse width high (t pclk_ch ) full 8 ns pclk period (t pclk ) full 16 ns propagation delay (t cpd , clk to pclk) full 0.1 ns rise time (t r ) (20% to 80%) 25c 0.2 ns fall time (t f ) (20% to 80%) 25c 0.2 ns data to pclk skew (t skew ) full 0.2 ns serial port output timing 2 sp_sdfs propagation delay (t dsdfs ) full 3 ns sp_sdo propagation delay (t dsdo ) full 3 ns serial port input timing sp_sdfs setup time (t ssf ) full 2 ns sp_sdfs hold time (t hsf ) full 2 ns fill input timing fill setup time (t sfill ) full 0.5 ns fill hold time (t hfill ) full 0.7 ns aperture delay (t a ) 25c 0.85 ns aperture uncertainty (jitter, t j ) 25c 80 fs rms 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and information about how these tests were completed. 2 5 pf loading.
ad6641 rev. 0 | page 8 of 28 spi timing requirements table 5. parameter description limit unit t ds setup time between the data and th e rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns min t dis_sdio time required for the sdio pin to sw itch from an output to an input relative to the sclk rising edge 10 ns min timing diagrams n?1 n n+2 n+3 n+4 n+5 n+1 clk+ clk? vin t a t ch t cl 09813-002 figure 2. input interface timing pd[11:0] output data bus t cpd t pclk t pclk_ch t skew clk+ clk? pclk+ pclk? 09813-003 figure 3. parallel cmos mo de output interface timing sp_sdfs sp_sclk t dsdfs 09813-004 figure 4. sp_sdfs propagation delay
ad6641 rev. 0 | page 9 of 28 sp_sclk sp_sdo d11 d10 t dsdo 09813-005 figure 5. sp_sdo propagation delay t ssf t hsf sp_sclk sp_sdfs 09813-006 figure 6. slave mode sp _sdfs setup/hold time clk fill t sfill t hfill 09813-007 figure 7. fill setup and hold times
ad6641 rev. 0 | page 10 of 28 absolute maximum ratings table 6. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +2.0 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?2.0 v to +2.0 v spi_vddio to avdd ?2.0 v to +2.0 v spi_vddio to drvdd ?2.0 v to +2.0 v pd[5:0] to drgnd ?0.3 v to drvdd + 0.2 v pclk to drgnd ?0.3 v to drvdd + 0.2 v pdor to drgnd ?0.3 v to drvdd + 0.2 v full to drgnd ?0.3 v to drvdd + 0.2 v clk to agnd ?0.3 v to avdd + 0.2 v fill to agnd ?0.3 v to drvdd + 0.2 v dump to agnd ?0.3 v to drvdd + 0.2 v empty to agnd ?0.3 v to drvdd + 0.2 v vin to agnd ?0.3 v to avdd + 0.2 v vref to agnd ?0.3 v to avdd + 0.2 v cml to agnd ?0.3 v to avdd + 0.2 v csb to drgnd ?0.3 v to spi_vddio + 0.3 v sp_sclk, sp_sdfs to agnd ?0.3 v to spi_vddio + 0.3 v sdio to drgnd ?0.3 v to spi_vddio + 0.3 v sp_sdo to drgnd ?0.3 v to spi_vddio + 0.3 v environmental storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed pad must be soldered to the ground plane for the lfcsp package. soldering the exposed pad to the pcb increases the reliability of the solder joints, maximizing the thermal capability of the package. table 7. package type ja jc unit 56-lead lfcsp_vq (cp-56-1) 23.7 1.7 c/w typical ja and jc are specified for a 4-layer board in still air. airflow increases heat dissipation, effectively reducing ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . esd caution
ad6641 rev. 0 | page 11 of 28 pin configurations and function descriptions full empty pd1? vin+ vin? avdd avdd avdd cml avdd avdd notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed pad is the only analog ground connection for the chip. it must be connected to pcb agnd. avdd avdd avdd vref avdd pdor? clk? avdd drvdd drgnd fill? fill+ dump clk+ avdd pclk? pclk+ dnc spi_vddio pd0? pd0+ pd1+ pd2? pd2+ drvdd drgnd pd3? pd3+ pd4? pd4+ pd5? pd5+ pdor+ sp_sdo dnc dnc dnc sp_sdfs sp_sclk drgnd drvdd sdio sclk csb dnc pin 1 indicator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 35 36 37 38 39 40 41 42 34 33 32 31 30 29 51 61 71 91 12 02 22 32 42 52 62 72 82 81 54 64 74 84 94 05 15 25 35 45 44 34 ad6641 55 65 top view (not to scale) 0 9813-008 figure 8. pin configuration for ddr lvds mode table 8. ddr lvds mode pin function descriptions pin no. mnemonic description 0 epad exposed pad. the exposed pad is the only grou nd connection for the chip. the pad must be connected to pcb agnd. 1 pd0? pd0 data output (lsb)complement. 2 pd0+ pd0 data output (lsb)true. 3 pd1? pd1 data outputcomplement. 4 pd1+ pd1 data outputtrue. 5 pd2? pd2 data outputcomplement. 6 pd2+ pd2 data outputtrue. 7, 24, 47 drvdd 1.9 v digital output supply. 8, 23, 48 drgnd digital output ground. 9 pd3? pd3 data outputcomplement. 10 pd3+ pd3 data outputtrue. 11 pd4? pd4 data outputcomplement. 12 pd4+ pd4 data outputtrue. 13 pd5? pd5 data output (msb)complement. 14 pd5+ pd5 data output (msb)true. 15 pdor? overrange outputcomplement. 16 pdor+ overrange outputtrue. 17 sp_sdo sport output. 18, 19, 20, 28, 54 dnc do not connect. do not connect to this pin. 21 sp_sdfs sport frame sync input (slave mode)/output (master mode). 22 sp_sclk sport clock input (slave mode)/output (master mode). 25 sdio serial port interface (spi) da ta input/output (serial port mode). 26 sclk serial port interface clock (serial port mode). 27 csb serial port chip select (active low). 29 spi_vddio 1.9 v or 3.3 v spi i/o supply. 30, 32, 33, 34, 37, 38, 39, 41, 42, 43, 46 avdd 1.9 v analog supply. 31 vref voltage reference input/output. nominally 0.75 v. 35 vin+ analog inputtrue. 36 vin? analog inputcomplement.
ad6641 rev. 0 | page 12 of 28 pin no. mnemonic description 40 cml common-mode output. enabled through the spi, this pin provides a reference for the optimized internal bias voltage for vin+ and vin?. 44 clk+ clock inputtrue. 45 clk? clock inputcomplement. 49 fill+ fifo fill input (lvds)true. 50 fill? fifo fill input (lvds)complement. 51 full fifo full output indicator. 52 empty fifo empty output indicator. 53 dump fifo readback input. 55 pclk? data clock outputcomplement. 56 pclk+ data clock outputtrue.
ad6641 rev. 0 | page 13 of 28 full empty pd0 vin+ vin? avdd avdd avdd cml avdd avdd avdd avdd avdd vref avdd pd10 clk? avdd drvdd drgnd fill? fill+ dump clk+ avdd pclk? pclk+ dnc spi_vddio dnc dnc pd1 pd2 pd3 drvdd drgnd pd4 pd5 pd6 pd7 pd8 pd9 pd11 sp_sdo dnc dnc dnc sp_sdfs sp_sclk drgnd drvdd sdio sclk csb dnc pin 1 indicator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 35 36 37 38 39 40 41 42 34 33 32 31 30 29 51 61 71 91 12 02 22 32 42 52 62 72 82 81 54 64 74 84 94 05 15 25 35 45 44 34 ad6641 55 65 top view (not to scale) 09813-009 1. dnc = do not connect. do not connect to this pin. 2. the exposed pad is the only analog ground connection for the chip. it must be connected to pcb agnd. figure 9. pin configuration for parallel cmos mode table 9. parallel cmos mode pin function descriptions pin no. mnemonic description 0 epad exposed pad. the exposed pad is the only grou nd connection for the chip. the pad must be connected to pcb agnd. 1, 2, 18, 19, 20, 28, 54 dnc do not connect. do not connect to this pin. 3 pd0 pd0 data output. 4 pd1 pd1 data output. 5 pd2 pd2 data output. 6 pd3 pd3 data output. 7, 24, 47 drvdd 1.9 v digital output supply. 8, 23, 48 drgnd digital output ground. 9 pd4 pd4 data output. 10 pd5 pd5 data output. 11 pd6 pd6 data output. 12 pd7 pd7 data output. 13 pd8 pd8 data output. 14 pd9 pd9 data output. 15 pd10 pd10 data output. 16 pd11 pd11 data output (msb). 17 sp_sdo sport output. 21 sp_sdfs sport frame sync input (slave mode)/output (master mode). 22 sp_sclk sport clock input (slave mode)/output (master mode). 25 sdio serial port interface (spi) da ta input/output (serial port mode). 26 sclk serial port interface clock (serial port mode). 27 csb serial port chip select (active low). 29 spi_vddio 1.9 v or 3.3 v spi i/o supply. 30, 32, 33, 34, 37, 38, 39, 41, 42, 43, 46 avdd 1.9 v analog supply. 31 vref voltage reference input/output. nominally 0.75 v. 35 vin+ analog inputtrue. 36 vin? analog inputcomplement. 40 cml common-mode output. enabled through the spi, this pin provides a reference for the optimized internal bias voltage for vin+ and vin?. 44 clk+ clock inputtrue.
ad6641 rev. 0 | page 14 of 28 pin no. mnemonic description 45 clk? clock inputcomplement. 49 fill+ fifo fill input (lvds)true. 50 fill? fifo fill input (lvds)complement. 51 full fifo full output indicator. 52 empty fifo empty output indicator. 53 dump fifo readback input. 55 pclk? data clock outputcomplement. 56 pclk+ data clock outputtrue.
ad6641 rev. 0 | page 15 of 28 typical performance characteristics avdd = 1.9 v, drvdd = 1.9 v, rated sample rate, t a = 25c, 1.5 v p-p differential input, a in = ?1 dbfs, unless otherwise noted. 0 ?20 ?40 ?60 0 20 40 60 80 100 120 frequency (mhz) 140 160 180 200 220 240 amplitude (dbfs) ?80 ?100 ?120 500msps 30.4mhz @ ?1.0dbfs snr: 64.9db enob: 10.7 bits sfdr: 87dbc 09813-010 figure 10. 16k point single-tone fft; 500 msps, 30.4 mhz 0 ?20 ?40 ?60 0 20 40 60 80 100 120 frequency (mhz) 140 160 180 200 220 240 amplitude (dbfs) ?80 ?100 ?120 500msps 100.4mhz @ ?1.0dbfs snr: 64.9db enob: 10.6 bits sfdr: 86dbc 09813-011 figure 11. 16k point single-tone fft; 500 msps, 100.4 mhz 0 ?20 ?40 ?60 0 20 40 60 80 100 120 frequency (mhz) 140 160 180 200 220 240 amplitude (dbfs) ?80 ?100 ?120 500msps 140.4mhz @ ?1.0dbfs snr: 64.7db enob: 10.6 bits sfdr: 84dbc 09813-012 figure 12. 16k point single-tone fft; 500 msps, 140.4 mhz 0 ?20 ?40 ?60 0 20 40 60 80 100 120 frequency (mhz) 140 160 180 200 220 240 amplitude (dbfs) ?80 ?100 ?120 491.52msps 368.0mhz @ ?1.0dbfs snr: 63.8db enob: 10.5 bits sfdr: 77dbc 09813-013 figure 13. 16k point single-tone fft; 491.52 msps, 368.0 mhz 0 ?20 ?40 ?60 0 20 40 60 80 100 120 frequency (mhz) 140 160 180 200 220 240 amplitude (dbfs) ?80 ?100 ?120 491.52msps 450.1mhz @ ?1.0dbfs snr: 63.3db enob: 10.4 bits sfdr: 76dbc 09813-014 figure 14. 16k point single-tone fft; 491.52 msps, 450.1 mhz 50 55 60 65 70 75 80 85 90 95 0 100 200 300 400 500 snr/sfdr (mhz) analog input frequency (mhz) sfdr (dbc), ?40c sfdr (dbc), +25c sfdr (dbc), +85c snr (dbfs), +85c snr (dbfs), +25c 09813-015 snr (dbfs), ?40c figure 15. single-tone snr/sfdr vs. input frequency (f in ) and temperature; 500 msps
ad6641 rev. 0 | page 16 of 28 50 55 60 65 70 75 80 85 90 95 250 300 350 400 450 500 550 snr/sfdr (db) s a m p l e r a t e ( m s p s ) sfdr @ 30.3mhz, 1.8v sfdr @ 30.3mhz, 1.9v sfdr @ 100.3mhz, 1.8v sfdr @ 100.3mhz, 1.9v snrfs @ 30.3mhz, 1.8v snrfs @ 30.3mhz, 1.9v snrfs @ 100.3mhz, 1.8v snrfs @ 100.3mhz, 1.9v 0 9813-116 s f d r ( d b c ) s n r ( d b f s ) figure 16. snr/sfdr vs. sample rate and supply 0 10 20 30 40 50 60 70 80 90 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (db) amplitude (db) snrfs, 1.9v snr, 1.9v sfdr, 1.9v sfdrfs, 1.9v snrfs, 1.8v snr, 1.8v sfdr, 1.8v sfdrfs, 1.8v snr (dbfs) sfdr (dbc) snr (db) sfdr (dbfs) 09813-117 figure 17. snr/sfdr vs. input amplitude; 500 msps,140.3 mhz ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?1 1023 2047 3071 4095 inl (lsb) output code 09813-018 figure 18. inl; 500 msps ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?1 1023 2047 3071 4095 dnl (lsb) output code 09813-019 figure 19. dnl; 500 msps 0 0.5 1.0 1.5 2.0 2.5 n?3 n?2 n?1 n n+1 n+2 1.24 lsb rms n+3 more number of hits (m) bins 09813-020 figure 20. grounded input histogram; 500 msps frequency (mhz) amplitude (dbfs) 0 25 50 75 100 125 150 175 200 225 ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 09813-021 491.52msps f in1 : 121.3mhz @ ?7dbfs f in2 : 124.7mhz @ ?7dbfs sfdr: 85dbc figure 21. 16k point single-tone fft; 491.52 msps, f in1 = 121.3 mhz, f in2 = 124.7 mhz
ad6641 rev. 0 | page 17 of 28 0 20 40 60 80 100 120 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr (db) amplitude (dbfs) sfdr, 1.9v sfdrfs, 1.9v imd3fs, 1.9v sfdr, 1.8v sfdrfs, 1.8v imd3fs, 1.8v imd3 (dbfs) sfdr (dbfs) sfdr (dbc) 09813-022 figure 22. two-tone sfdr vs. input amplitude; 500 msps, 119.2 mhz, 122.5 mhz 0 20 40 60 80 100 120 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr (db) amplitude (dbfs) sfdr, 1.9v sfdrfs, 1.9v imd3fs, 1.9v sfdr, 1.8v sfdrfs, 1.8v imd3fs, 1.8v imd3 (dbfs) sfdr (dbfs) sfdr (dbc) 09813-023 figure 23. two-tone sfdr vs. input amplitude; 500 msps, 139.3 mhz, 141.3 mhz 50 55 60 65 70 75 80 85 90 1.75 1.80 1.85 1.90 1.95 2.00 snr/sfdr (db) power supply (v) 09813-024 snr (dbfs) sfdr (dbc) figure 24. snr/sfdr vs. power supply 0 100 200 300 400 500 600 700 800 0 50 100 150 200 250 300 350 400 250 300 350 400 450 500 550 power (mw) current ( m a) sample rate (msps) 09813-025 total power i avdd i drvdd figure 25. current and power vs. sample rate
ad6641 rev. 0 | page 18 of 28 equivalent circuits dc 500? 500? spi controlled v boost cml avdd v in+ avdd v in? avdd a in+ a in? 09813-016 figure 26. dc equivalent analog input circuit 1k? 1.3pf vin? v in+ 09813-017 figure 27. ac equivalent analog input circuit 0.9v 15k ? 15k ? clk+ or fill+ clk? or fill? a v dd 09813-127 avdd avdd figure 28. equivalent clk and fill input circuit 09813-128 dr v dd drgnd figure 29. equivalent pd[11:0], full, empty, pclk, and sp_sdo output circuit dr v dd output+ v? v+ o utput? v+ v? 0 9813-110 figure 30. lvds outputs (pdor, pd[5:0], pclk) s clk 350 ? 30k ? 09813-129 dr v dd dvdd figure 31. equivalent sclk input circuit csb 350? 30k? 09813-130 dr v dd drvdd drvdd figure 32. equivalent csb input circuit s dio ctrl 30k ? 09813-131 drvdd dr v dd 350 ? figure 33. equivalent sdio circuit
ad6641 rev. 0 | page 19 of 28 sp_sdfs/ sp_sclk ctrl master/slave 30k? 0 9813-132 dr v dd 350? figure 34. equivalent sp_sdfs and sp_sclk circuit 20k ? not used spi ctrl vref select 00: internal vref 01: imort vref 10: export vref 11: not used (01) (10) (00) avdd vref (11) 09813-133 figure 35. equivalent vref circuit
ad6641 rev. 0 | page 20 of 28 spi register map table 10. memory map register addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 0x00 chip_port_config 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles should be mirrored by the user so that lsb or msb first mode registers correctly, regardless of shift mode. 0x01 chip_id 8-bit chip id, bits[7:0] = 0xa0 read only default is unique chip id, different for each device. this is a read-only register. 0x02 chip_grade 0 0 speed grade: 10 = 500 msps x 1 x 1 x x 1 x x 1 read only child id used to differentiate graded devices. transfer register 0xff device_update [7:1] = 0000000 sw transfer 0x00 synchro- nously transfers data from the master shift register to the slave. adc functions 0x08 modes 0 0 0 0 0 inte rnal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = reserved 0x00 determines various generic modes of chip operation. 0x0d test_io (for user-defined mode only, set bits[3:0] = 1000) 00 = pattern 1 only 01 = toggle pattern 1/ pattern 2 10 = toggle pattern 1/0000 11 = toggle pattern 1/ pattern 2/0000 reset pn23 gen: 1 = on 0 = off (default) reset pn9 gen: 1 = on 0 = off (default) output test mode: 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checkerboard output 0101 = pn23 sequence 0110 = pn9 0111 = one/zero word toggle 1000 = user defined 1001 = unused 1010 = unused 1011 = unused 1100 = unused (format determined by output_mode) 0x00 when set, the test data is placed on the output pins in place of normal data. set pattern values: pattern 1: reg 0x19, reg 0x1a pattern 2: reg 0x1b reg 0x1c. 0x14 output_mode 0 0 0 output disable: 0 = enable (default) 1 = disable 0 = cmos: 1 = lvds (default) output invert: 1 = on 0 = off (default) data format select: 00 = offset binary (default) 01 = twos complement 10 = gray code 11 = reserved 0x08
ad6641 rev. 0 | page 21 of 28 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x15 output_adjus t [7:4] = 0000 lvds course adjust: 0 = 3.5 ma (default) 1 = 2.0 ma lvds fine adjust: 001 = 3.50 ma 010 = 3.25 ma 011 = 3.00 ma 100 = 2.75 ma 101 = 2.50 ma 110 = 2.25 ma 111 = 2.00 ma 0x00 0x16 output_phase output clock polarity: 1 = inverted 0 = normal (default) [6:0] = 0000000 0x03 0x17 output_delay 0 0 0 0 output clock delay: 0000 = 0 0001 = ?1/10 0010 = ?2/10 0011 = ?3/10 0100 = reserved 0101 = +5/10 0110 = +4/10 0111 = +3/10 1000 = +2/10 1001 = +1/10 0 shown as fractional value of sampling clock period that is subtracted or added to initial t skew , see figure 3 ). 0x18 input range vref select: 00 = internal v ref (20 k pull-down) 01 = import v ref (0.59 v to 0.80 v on vref pin) 10 = export v ref 11= not used 0 input voltage range setting (v): 11100 = 1.60 11101 = 1.58 11110 = 1.55 11111 = 1.52 00000 = 1.50 00001 = 1.47 00010 = 1.44 00011 = 1.42 00100 = 1.39 00101 = 1.36 00110 = 1.34 00111 = 1.31 01000 = 1.28 01001 = 1.26 01010 = 1.23 01011= 1.20 01100 = 1.18 0 0x19 user_patt1_lsb [7:0] 0 user defined pattern 1 lsb. 0x1a user_patt1_msb [7:0] 0 user defined pattern 1 msb. 0x1b user_patt2_lsb [7:0] 0 user defined pattern 2 lsb. 0x1c user_patt2_msb [7:0] 0 user defined pattern 2 msb. digital controls 0x101 fill control register reserved fill input pin disable reserved lifo mode fifo fill mode: 00 = single 01 = continuous 1x = reserved reserved standby after fill 0 0x102 fifo config [7:4] = reserved dump reset fill reset dump fill 0 0x104 fill count [7:0] 0x7f number of words to use for fill or dump.
ad6641 rev. 0 | page 22 of 28 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x105 settle count0 [7:0] 0 lsbs settling time given to adc before initiating fill. 0x106 settle count1 [7:0] 0 msbs settling time given to adc before initiating fill. 0x107 dump control [7:3] = reserved 0 = slave 1 = master readback mode: 00 = off 01 = parallel 10 = sport 11 = reserved 0 customer drives sp_sclk, sp_sdfs in slave mode. 0x10a fifo status [7:3] = reserved over- range empty full 0 0x10b fifo dump data0 [7:0] = lsbs 0 lsbs readback data. 0x10c fifo dump data1 [7:4] = rese rved [3:0] = msbs 0 msbs upper four bits readback data. 0x10f read offset data0 [7:0] = lsbs 0 lsbs offset to ram, allowing subsegments of data cap- ture to be read. 0x110 read offset data1 [7:6] = rese rved [5:0] = msbs 0 msbs offset. 0x111 pport control [7:5] = reserved divide ratio = 2 (bit word): 00100 = divide by 8 (default) 01111 = divide by 30 1xxxx = divide by 32 0x04 cmos parallel port divide rate. 0x112 sport control [7:5] = reserved divide ratio= 2 (bit word): 00100 = divide by 8 (default) 01111 = divide by 30 1xxxx = divide by 32 0x04 serial port divide rate. 0x13a fifo test bist [7:5] = reserved sets the bist mode for the fifo: 1xxx = reserved 0111 = reserved 0110 = 12'hfff (?1 lsb) 0101 = 12'h001 (+1 lsb) 0100 = pn data 0011 = checkerboard (12'haaa, 12'h555, 12'haaa, ) 0010 = checkerboard (12'h555, 12'haaa, 12'h555, ) 0001 = decrementing ramp 0000 = incrementing ramp fifo bist enable 0 1 x = dont care.
ad6641 rev. 0 | page 23 of 28 theory of operation the on-chip fifo allows small snapshots of time to be captured via the adc and read back at a lower rate. this reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. fifo operation the capture of the data can be signaled through writes to the spi port by pulsing the fill pins. the transaction diagram shown in figure 36 illustrates the loading of the fifo. at event 1, the fifo is instructed to fill either by asserting the fill pins or via a write to the spi bits. fill pin operation can be delayed by a programmable fill hold-off counter so that the fifo data can be surrounding a fill event. the fifo then loads itself with data. the number of samples of data is determined by the spi fill count register (0x104). this is an 8- bit register with values from 0 to 255. the number of samples placed in the fifo is determined by the following equation: number of samples = ( fill_cnt + 1) 64 after the fifo has begun filling at event 2, the ad6641 asserts a full flag to indicate that the fifo has finished capturing data and enters a wait state in which the device waits to receive the dump instruction from the dump pin or the spi. after the data has been shifted (event 4), the fifo goes into the idle state and waits for another fill command. during the idle state, the adc can optionally be placed into standby mode to save power. if the adc powers down in the idle state, initiating a fill operation (event 1) powers up the adc. in this mode, the adc waits for settle count cycles (0x105, 0x106) before capturing the data. settle count is programmable from the spi port and allows the analog circuitry to stabilize before taking data. an intelligent trade-off between speed of acquisition and accuracy can be made by using this register. the data can be read back through any of the three output inter- faces at a low data rate, which further saves power. if the spi or sport is used to read back the data, the interface can require as few as three pins. a full flag and an empty flag are provided to signal the state of the fifo. the fifo status register (0x10a) in the spi also allows this to be monitored via software. single capture mode the fifo can be placed into single capture mode by writing the fifo fill mode bits in the fill control register (0x101[3:2]) to 00. in the single capture mode, the user initiates a capture either by driving the fill pins high or by initiating a fill command through the spi port by writing the standby after fill bit (0x101[0]). this powers up the adc (if needed) after a programmable amount of time as determined by the spi settle count registers (0x105, 0x106). if bit 0 of the 0x101 register in the spi is set, the adc returns to standby mode after the capture is complete. fill pin timing a fill of the fifo can be initiated by asserting the differential fill pins. when a pulse is detected on the fill pins, the fifo is filled. dump pin timing a readback of the fifo can be initiated by asserting the dump pin. when a logic high is detected on the dump pin, the fifo data is available through the chosen interface. 09813-034 1 2 3 4 events filling fifo with data wait for dump (optional) idle state start sp_sclk and sp_sdfs shift data idle state state figure 36. on-chip fifo transactio n timing assuming serial port clk+ clk? fill+, fill? 09813-035 figure 37. fifo fill timing 09813-036 clk+ clk? dump figure 38. fifo dump timing
ad6641 rev. 0 | page 24 of 28 sport master mode (single capture) details of the transaction diagram for serial master mode are shown in figure 39 for single capture mode with the sdo output. clock cycles are approximate because the fill and dump signals can be driven asynchronously. in this example, sclk is derived from the master clock with a divide by 8 programmed from the spi. fill pulse (1) the fifo captures data after a fill signal (high level) is detected on the rising edge of the sampling clock. in synchronous opera- tion, a valid high level is accomplished by adhering to the setup and hold times specified. for nonsynchronous control, the fill signal can be widened to accommodate two or more clock cycles to guarantee capture of a high level. fill count (0x104) is reset on the rising edge of the clock and is incremented on subsequent clock cycles only after the fill signal returns low. a new fill signal at any point during the capture resets the counter and begins filling the fifo. empty signal (2) after the fifo state machine has begun loading data, the empty signal goes low 24 clock cycles after the fill signal was last sampled high. full signal (3) the full signal indicates when the fifo has been filled and is driven high when the number of samples specified has been captured in the fifo, where number of samples = ( fill_cnt + 1) 64 the time at which the full signal goes high is based on (fill_cnt + 1) 64 + 13 clock cycles after the fill signal was last sampled high. dump signal (4)transition to high the dump signal initiates reading data from the fifo. dump is enabled with a high level and should be initiated only after the full signal goes high. the dump signal should be held high until all data has been read out of the fifo. sclk signal (5) the sclk (serial clock) signal is configured as an output from the device when in the master mode of operation. sclk begins cycling five adc clock cycles after the dump signal is sampled high and continues cycling up until one additional cycle after the empty signal goes high. sclk then remains low until the next dump operation. sdfs signal (6) the sdfs (serial data frame sync) signal is configured as an output from the device when in the master mode of operation. frame synchronization begins 15 adc clock cycles after the dump signal is sampled. dump signal (7)transition to low a dump signal transition to low is applied after data has been read out of the fifo. empty signal (8)transition to high the empty signal transitions to high after data has been output from the fifo based on the clock cycle count of (fill_cnt + 1) 64. the transition occurs 76 adc clock cycles after the last lsb(s) of data have been output on the serial port. fill 1 2 3 4 5 6 7 8 empty full dump sclk sdfs sdo 09813-037 figure 39. sport master mode transaction diagram
ad6641 rev. 0 | page 25 of 28 parallel master mode (single capture) details of the transaction diagram for parallel master mode are shown in figure 40 with the pd[11:0] output word. clock cycles are approximate because the fill and dump signals can be driven asynchronously. in this example, pclk is derived from the master clock with a divide by 8 programmed from the spi. fill pulse (1) the fifo captures data after a fill signal (high level) is detected on the rising edge of the sampling clock. in synchronous opera- tion, a valid high level is accomplished by adhering to the setup and hold times specified. for nonsynchronous control, the fill signal can be widened to accommodate two or more clock cycles to guarantee capture of a high level. fill count (0x104) is reset on the rising edge of the clock and is incremented on subsequent clock cycles only after the fill signal returns low. a new fill signal at any point during the capture resets the counter and begins filling the fifo. empty signal (2) after the fifo state machine has begun loading data, the empty signal goes low 24 clock cycles after the fill signal was last sampled high. full signal (3) the full signal indicates when the fifo has been filled and is driven high when the number of samples specified has been captured in the fifo, where number of samples = ( fill_cnt + 1) 64 the time at which the full signal goes high is based on (fill_cnt + 1) 64 + 13 clock cycles after the fill signal was last sampled high. dump signal (4)transition to high the dump signal initiates reading data from the fifo. dump is enabled with a high level and should be initiated only after the full signal goes high. the dump signal should be held high until all data has been read out of the fifo. pclk signal (5) the pclk (parallel clock) signal is configured as an output from the device. pclk begins cycling 71 adc clock cycles after the dump signal is sampled high. pclk goes low after the last data is read out of the fifo and remains low until the next dump operation. pd[11:0] signal (6) the pd (parallel data) output provides 12 data bits (pd[11:0]) at a maximum rate of 1/8 th of the sampling clock. data begins after two pclk cycles (assuming the dump signal has been sampled). dump signal (7)transition to low a dump signal transition to low is applied after data has been read out of the fifo. empty signal (8)transition to high the empty signal transitions to high after data has been output from the fifo based on the clock cycle count of (fill_cnt + 1) 64. the transition occurs nine clock cycles after the last pclk rising edge. continuous capture mode the fifo can be placed into continuous capture mode by writ- ing the fifo fill mode bits in the fill control register (0x101[3:2]) to 01. in the continuous capture mode, data is loaded continu- ously into the fifo and the fill pins pulsing high is used to stop the operation. this allows the history of the samples that preceded an event to be captured. fill empty full dump pclk+ pclk? pd[11:0] 0 9813-038 1 2 3 4 5 6 7 8 d0 d8 d16 figure 40. parallel mode transaction diagram
ad6641 rev. 0 | page 26 of 28 fifo output interfaces the fifo data is available through one of three interfaces. the data can be output on the serial data port (sport), the spi port, or a 12-bit cmos interface. the data port chosen must be selected from the spi port before the data is read from the fifo. only one interface can be chosen at a time. the sport and spi interfaces are powered via the spi_vddio pin and can support either 1.9 v or 3.3 v logic levels. sport interface the sport consists of a clock (sp_sclk) and frame sync (sp_sdfs) signal. the sp_sclk and sp_sdfs signals are output from the ad6641 when the sport is configured as a bus master and are input to the device when it is configured as a slave port. serial data frame (serial bus master) the serial data transfer is initiated with sp_sdfs. in master mode, the internal serial controller initiates sp_sdfs after the dump input goes high requesting the data. sp_sdfs is valid for one complete clock cycle prior to the data shift. on the next clock cycle, the ad6641 begins shifting out the data stream. cmos output interface the data stored in the fifo can also be accessed via a 12-bit parallel cmos interface. the maximum output throughput supported by the ad6641 is in the 12-bit cmos mode and is internally limited to 1/8 th of the maximum input sample rate. therefore, the output maximum output data rate is 62.5 mhz at a 500 msps input sample rate. see figure 3 for the parallel cmos mode output interface timing diagram. lvds output interface the ad6641 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option similar to the ieee 1596.3 standard using the spi. this lvds standard can further reduce the overall power dissipation of the device, which reduces the power by ~39 mw. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv differential or 700 mv p-p swing at the receiver. the ad6641 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. no far-end receiver termination and poor differential trace routing may result in timing errors. it is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. the data on the lvds output port is interleaved in a msb/lsb format. pclk is generated by dividing the adc sample clock by the programmed decimation rate (8 to 32, even divides). the maximum rate of pclk is limited to 62.5 mhz. sp_sclk sp_sdfs sp_sdo 4 8 12 16 20 24 28 d1 d3 d2 0 0 9813-039 figure 41. data output in serial bus master mode pclk? pclk+ d0[11:6] d0[5:0] d8[11:6] d8[5:0] d16[11:6] d16[5:0] d24[11:6] d24[5:0] x pd[5:0] lsb/msb d0 sample lsb/msb d8 sample 09813-040 figure 42. ddr lvds output msb/lsb interleaving with decimate by 8
ad6641 rev. 0 | page 27 of 28 analog input and voltage reference the analog input to the ad6641 is a differential buffer. for best dynamic performance, match the source impedances driving vin+ and vin? such that common-mode settling errors are symmetrical. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single- ended signal. a wideband transformer, such as mini-circuits? adt1-1wt, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip reference to a nominal 1.7 v. an internal differential voltage reference creates positive and negative reference voltages that define the 1.5 v p-p fixed span of the adc core. this internal voltage reference can be adjusted by means of an spi control. vref the ad6641 vref pin (pin 31) allows the user to monitor the on-board voltage reference or provide an external reference (requires configuration through the spi). the three optional settings are internal v ref (pin is connected to 20 k to ground), export v ref , and import v ref . do not attach a bypass capacitor to this pin. vref is internally compensated and additional loading may impact performance. configuration using the spi three pins define the spi of the ad6641: sclk, sdio, and csb (see table 11 ). sclk (a serial clock) is used to synchronize the read and write data presented from and to the ad6641. sdio (serial data input/output) is a bidirectional pin that allows data to be sent to and read from the internal memory map registers. csb (chip select) is an active low control that enables or disables the read and write cycles. table 11. serial port interface pins pin function sclk serial clock. serial shift cl ock input. sclk is used to synchronize serial interface reads and writes. sdio serial data input/ output. bidirectional pin that serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select (active low). this control gates the read and write cycles. the falling edge of the csb pin, in conjunction with the rising edge of the sclk pin, determines the start of the framing. an example of the serial timing can be found in figure 43 (for symbol definitions, see table 5 ). csb can be held low indefinitely, which permanently enables the device; this is called streaming. csb can stall high between bytes to allow additional external timing. when csb is tied high, spi functions are placed in high impedance mode. during an instruction phase, a 16-bit instruction is transmitted. the first bit of the first byte in a serial data transfer frame indicates whether a read command or a write command is issued. data follows the instruction phase, and its length is determined by the w0 and w1 bits. all data is composed of 8-bit words. the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. if the instruction is a read operation, the serial data input/output (sdio) pin changes direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb first mode. msb first is the default mode on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note, interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1w0a12a11a10a9a8a7 d5d4d3d2d1d0 t low t high 09813 -073 figure 43. serial port interface timing diagram
ad6641 rev. 0 | page 28 of 28 outline dimensions compliant to jedec standards mo-220-vlld-2 030509-a pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 6.25 6.10 sq 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0 .85 0 .80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.25 min exposed pad (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 44. 56-lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp-56-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad6641bcpz-500 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-1 ad6641bcpzrl7-500 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq], 7 tape and reel cp-56-1 AD6641-500EBZ evaluation board 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09813-0-4/11(0)

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